The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Mar. 04, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Namkyu Cho, Suwon-si, KR;

Jungtaek Kim, Suwon-si, KR;

Moonseung Yang, Suwon-si, KR;

Sumin Yu, Suwon-si, KR;

Seojin Jeong, Suwon-si, KR;

Seokhoon Kim, Suwon-si, KR;

Pankwi Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 64/258 (2025.01);
Abstract

A semiconductor device includes an active region extending on a substrate in a first direction, a plurality of channel layers on the active region to be spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, the plurality of channel layers including silicon germanium, a gate structure intersecting the active region and the plurality of channel layers on the substrate to surround the plurality of channel layers, respectively, a source/drain region on the active region on at least one side of the gate structure, the source/drain region in contact with the plurality of channel layers, and a substrate insulating layer disposed between the source/drain region and the substrate. The source/drain region includes a first layer in contact with a side surface of the gate structure, side surfaces of the plurality of channel layers, and an upper surface of the substrate insulating layer.


Find Patent Forward Citations

Loading…