The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Nov. 27, 2023
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Nereo Markulic, Etterbeek, BE;

Jan Craninckx, Boutersem, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01); H03M 1/06 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1245 (2013.01); H03M 1/0614 (2013.01);
Abstract

An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (V) and for outputting an output signal (V), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.


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