The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Oct. 30, 2023
Marvell Asia Pte Ltd, Singapore, SG;
Quanli Lu, Irvine, CA (US);
Liang Fan, Irvine, CA (US);
Afshin Mellati, Irvine, CA (US);
Espen Olsen, Irvine, CA (US);
Linghsiao Wang, Irvine, CA (US);
Cindra Abidin, Irvine, CA (US);
MARVELL ASIA PTE LTD, Singapore, SG;
Abstract
A circuit includes a plurality of differential pairs of transistors and circuitry connected to the plurality of differential pairs of transistors. The plurality of differential pairs of transistors is configured to receive a first clock and a second clock and to generate an output representing an exclusive OR sum of the first and second clocks. The circuitry is configured to compensate for mismatch between the plurality of differential pairs of transistors so that the output is zero when the first and second clocks are in quadrature with each other and the output is non-zero when the first and second clocks are not in quadrature with each other regardless of mismatch between the plurality of differential pairs of transistors.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile