The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Jan. 22, 2024
Applicant:

Movellus Circuits Incorporated, San Jose, CA (US);

Inventors:

Marcus Van Ierssel, Toronto, CA;

Jeffrey Alan Fredenburg, Chicago, IL (US);

Assignee:

Movellus Circuits Inc., Ann Arbor, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/14 (2014.01); G01R 31/317 (2006.01); G06F 1/08 (2006.01); H03L 7/081 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H03K 5/14 (2013.01); G01R 31/31727 (2013.01); G06F 1/08 (2013.01); H03L 7/0812 (2013.01); H03K 2005/00058 (2013.01);
Abstract

A timing margin sensor includes a delay circuit to generate a calibrated delay that corresponds to a known delay value of a logic circuit. Circuitry locks a first delay produced by the delay circuit to a clock period of a clock signal that is associated with the known delay value. A programmable selector adjusts the first delay to generate the calibrated delay, the calibrated delay including a timing margin component. Circuitry detects a change in supply voltage provided to the logic circuit based on a detected change in the calibrated delay. Clock adjustment circuitry selectively changes the clock period based on the detected change in the calibrated delay.


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