Stacked memory and manufacturing method therefor

Abstract

Provided is a stacked memory with an improved yield rate and with which suitable operation timing control is possible. Also provided is a manufacturing method therefor. Provided is a stacked memoryobtained by stacking a plurality of memory chips, wherein the memory chips each include a plurality of memory cells, and comprise: a memory unitthat is capable of storing data and has a normal memory blockused mainly for reading and writing data and a spare memory blocksubstituted for a defective memory cell in the normal memory block; an address storage unitthat, for each of two or more stacked memory chips, stores a slice address identifying a memory chip serving as an object to undergo substitution of the normal memory blockwith the spare memory blockas a substitution source slice address, and stores a memory address serving as the object to undergo substitution as a substitution source memory address; a comparison unitthat compares a request address indicating the slice address and memory address of an access request destination, and the substitution source address; a specification unitthat, on the basis of the comparison results, specifies the memory unitthat is actually to be accessed and generates an access timing; a timing control unitthat selects one from among the generated access timing and access timings transmitted from the other memory chips, and controls access to the memory unitat the selected access timing; and an execution unitthat executes reading and writing to the specified memory unitat the selected access timing.