The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Dec. 08, 2023
Apple Inc., Cupertino, CA (US);
Robert E. Jeter, Santa Clara, CA (US);
Jean-Didier Allegrucci, Sunnyvale, CA (US);
Jingkui Zheng, Sunnyvale, CA (US);
Kai Lun Hsiung, Fremont, CA (US);
Venkata Ramana Malladi, Santa Clara, CA (US);
Srinivasa Rao Masanam, Cedar Park, TX (US);
Alma L. Juarez Dominguez, Campbell, CA (US);
Moosa Yahyazadeh, Milpitas, CA (US);
Karthik Vathool Jambunatha Ramani, Sunnyvale, CA (US);
Prerana P. Sarode, St Albans, GB;
Satish B. Dulam, Sunnyvale, CA (US);
Brooke E. Benzenberg, Sunnyvale, CA (US);
Rahul Ranjan, Campbell, CA (US);
Naveen Kumar Korada, Round Rock, TX (US);
Apple Inc., Cupertino, CA (US);
Abstract
A memory controller is configured to communicate with a memory. The memory controller includes a calibration control circuit configured to perform calibrations of memory signals conveyed between the memory controller and the memory. A storage circuit is configured to store results of the calibrations, including voltage and timing margins of the memory signals. A monitoring circuit is configured to access results of the calibrations stored in the storage circuit to determine whether a set of calibration metrics are being met or exceeded during a period of time. In response to the set of calibration metrics being met or exceeded during the period of time, the monitoring circuit is configured to cause the calibration control circuit to operate in a reduced calibration mode that reduces an amount of time the calibration control circuit spends performing one or more subsequent calibrations.