The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2026

Filed:

Dec. 15, 2022
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Sharukh Shahajahan Shaikh, San Jose, CA (US);

Arun Kumar, Mountain View, CA (US);

Kun Xu, Austin, TX (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 115/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2115/02 (2020.01);
Abstract

Techniques are provided for congestion aware placement of the fabric components of an interconnect in an integrated circuit device. A floorplan of the interconnect is projected on a virtual grid that includes placement locations for the fabric components. Locations of the fabric components can be initialized with the placement locations of the virtual grid. Updated locations for the placement of each of the fabric components on the virtual grid can be determined based on minimization of a total wirelength (TWL) cost function of all the nets in the interconnect. Timing slices are inserted in the interconnect after the placement of the fabric components at the updated locations. The floorplan information with the placement information of the fabric components and the timing slices can be used for the physical design of the interconnect to provide a timing clean result.


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