The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2026
Filed:
Apr. 29, 2024
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Chang Liu, Irvine, CA (US);
Xiaoliang Li, Irvine, CA (US);
Boyu Hu, Irvine, CA (US);
Delong Cui, Tustin, CA (US);
Jun Cao, Irvine, CA (US);
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Abstract
A low latency gearbox retimer architecture is provided. An apparatus includes a first clock generator configured to generate a first clock signal having a first frequency, and a second clock signal having a second frequency. A control logic is configured to generate the control signal, based, at least in part, on the second clock signal, and two or more analog to digital converter (ADC) slices. Each respective ADC slice includes a multiplexer having a first number of inputs and a second number of outputs, wherein the multiplexer is configured to select a set of the second number of inputs to be output, wherein the set of the second number of inputs selected is based, at least in part, on a control signal. The apparatus includes one or more unit-ADCs, wherein the respective outputs of the one or more unit-ADCs are coupled to the multiplexer as an input.