The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jun. 18, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sanggil Lee, Ansan-si, KR;

Seokhoon Kim, Suwon-si, KR;

Sungmin Kim, Incheon, KR;

Jungtaek Kim, Yongin-si, KR;

Pankwi Park, Incheon, KR;

Dongsuk Shin, Suwon-si, KR;

Namkyu Cho, Yongin-si, KR;

Ryong Ha, Seoul, KR;

Yang Xu, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/69 (2025.01); H10D 62/822 (2025.01); H10D 64/27 (2025.01); H10D 64/66 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H10D 30/797 (2025.01); H10D 62/822 (2025.01); H10D 64/311 (2025.01); H10D 64/66 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01);
Abstract

Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.


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