Memory device implementing unified memory architecture integrating multiple memory types

Abstract

A semiconductor memory device is formed on a semiconductor substrate including a first memory region, a second memory region and a logic region. A flash memory array is formed in the first memory region and includes an array of magnetoresistive random-access (MRAM) memory cells, each MRAM memory cell including an access transistor coupled to a magnetic tunnel junction (MTJ) storage element. A read-only (ROM) memory array is formed in the second memory region and includes an array of read-only (ROM) memory cells, each ROM memory cell including an access transistor coupled to a short or open circuit as the ROM storage element. A memory peripheral circuit is formed in the logic region. The memory peripheral circuit includes control circuits for receiving input commands and executing memory operations to the memory cells in the flash memory array and the read-only memory array.