Phase interpolator, clock data recoverer, communication device, and operating method of phase interpolator

Abstract

A phase interpolator includes a decoder, a digital-to-analog converter, and a first phase mixer. The decoder is configured to output a digital signal based on a control signal. The digital-to-analog converter is configured to, based on a first current, a second current, and the digital signal, adjust first to third weight signals among a plurality of target weight signals and to output the first to third weight signals. The first phase mixer is configured to determine first and second target clock signals among a plurality of input clock signals, and based on the first to third weight signals, generate a first output clock signal having a phase between the first and second target clock signals as a phase interpolation clock signal.