Circuits and methods for phase interpolators and generating quadrature clock signals

Abstract

Phase interpolators are provided, the phase interpolators including: a first phase interpolator having a first output that outputs a first interpolated clock signal based on quadrature clock signals and a first phase interpolator control signal; a second phase interpolator having a second output that outputs a second interpolated clock signal based on the quadrature clock signals and a second phase interpolator control signal that is shifted from the first phase interpolator control signal by half of an integral nonlinearity (INL) period of the first phase interpolator; and a phase combiner that outputs a third interpolated clock signal based on the first interpolated clock signal and the second interpolated clock signal. In some of these embodiments, the phase interpolators further comprise a first amplitude limiter that receives the first interpolated clock signal and outputs a first amplitude-limited interpolated clock signal that is provided to the phase combiner.