The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Nov. 30, 2023
Applicant:

Analog Devices, Inc., Wilmington, MA (US);

Inventors:

Wei Wang, Colorado Springs, CO (US);

Thomas A Spargo, Colorado Springs, CO (US);

Michael E. Harrell, Colorado Springs, CO (US);

Angel Rael, Colorado Springs, CO (US);

Assignee:

Analog Devices, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); H03K 3/356 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/00384 (2013.01); H03K 3/356017 (2013.01); H03K 19/018514 (2013.01);
Abstract

Various techniques are described to level shift an input signal from an input node to an output node of an open-loop voltage buffer circuit so that a DC offset voltage and a temperature-dependent voltage from the level shifter circuitry are mutually canceled out. By using these techniques, the output voltage of the buffer circuit tracks the input voltage with no DC offset voltage and no temperature drift.


Find Patent Forward Citations

Wang, Wei. (2026). Buffer circuit with threshold voltage cancellation (U.S. Patent No. 12537525). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12537525

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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