The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Mar. 28, 2023
Applicants:

SK Hynix Inc., Icheon, KR;

Korea Advanced Institute of Science and Technology, Daejeon, KR;

Inventors:

Jung Woo Lee, Icheon, KR;

Yang Kyu Choi, Seoul, KR;

Ji Man Yu, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/34 (2006.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
G11C 16/3404 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/694 (2025.01); H10D 62/121 (2025.01);
Abstract

A nonvolatile memory device and an operating method thereof are disclosed. An operating method of a nonvolatile memory device may comprise providing the nonvolatile memory device including a memory transistor, the memory transistor including a source, a drain, a channel disposed between the source and the drain, and a first insulating layer, a charge storage layer, a second insulating layer, and a gate which are sequentially disposed on the channel, and curing the memory transistor by removing charges or traps existing at least at an interface between the channel and the first insulating layer by generating a gate induced drain leakage (GIDL) current on the drain side of the memory transistor and using Joule heating caused by the GIDL current.


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Lee, Jung. (2026). Nonvolatile memory device and operation method thereof (U.S. Patent No. 12537066). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12537066

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