The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jul. 25, 2023
Applicant:

Sunrise Memory Corporation, San Jose, CA (US);

Inventor:

Eli Harari, Saratoga, CA (US);

Assignee:

SUNRISE MEMORY CORPORATION, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01); H01L 21/02 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10D 1/00 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 30/69 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/68 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
G11C 16/0466 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/0416 (2013.01); G11C 16/0483 (2013.01); G11C 16/0491 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/28 (2013.01); G11C 16/3427 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/32133 (2013.01); H01L 21/76892 (2013.01); H01L 23/528 (2013.01); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10D 1/00 (2025.01); H10D 30/0321 (2025.01); H10D 30/0413 (2025.01); H10D 30/6728 (2025.01); H10D 30/693 (2025.01); H10D 30/694 (2025.01); H10D 62/115 (2025.01); H10D 62/151 (2025.01); H10D 62/292 (2025.01); H10D 62/40 (2025.01); H10D 62/83 (2025.01); H10D 64/037 (2025.01); H10D 64/685 (2025.01); H10D 64/693 (2025.01); H10D 88/00 (2025.01);
Abstract

A memory structure including a storage transistor having a data storage storage region, a gate terminal, a first drain or source terminal, and a second drain or source terminal, the storage transistor being configurable to have a threshold voltage that is representative of data stored in the data storage region; a word line electrically connected to the gate terminal, configured to provide a control voltage during a read operation; a bit line electrically connecting the first drain or source terminal to data detection circuitry; and a source line electrically connected to the second drain or source terminal, configured to provide a capacitance sufficient to sustain at least a predetermined voltage difference between the second drain or source terminal and the gate terminal during the read operation.


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