Embedded memory device, integrated circuit having the same and method of operating the same

Abstract

An embedded memory device includes a retention voltage supply circuit outputting a retention voltage in response to a retention activation signal, and a plurality of array voltage supply circuits outputting corresponding array voltages to corresponding bit cells. The plurality of array voltage supply circuits respectively include an array switch providing the retention voltage as a corresponding array voltage in response to the retention activation signal, a power switch providing a power supply voltage as the corresponding array voltage in response to a power gate activation signal, and an auxiliary circuit compensating the corresponding array voltage during a write operation or a read operation.