The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2026

Filed:

Jul. 30, 2024
Applicant:

Rain Neuromorphics Inc., San Francisco, CA (US);

Inventors:

Nawab Ali, Bellingham, WA (US);

Muzaffer Kal, Redmond, WA (US);

Alexander Almela Conklin, San Jose, CA (US);

Burak Erbagci, San Jose, CA (US);

Cagri Eryilmaz, San Francisco, CA (US);

Mohammed Elneanaei Abdelmoneem Fouda, Irvine, CA (US);

Assignee:

RAIN NEUROMORPHICS INC., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 13/28 (2013.01); G06F 2213/28 (2013.01);
Abstract

A compute tile is described. The compute tile includes compute engines and a general-purpose (GP processor coupled with the compute engines. Each of the compute engines includes a compute-in-memory (CIM) hardware module. The CIM hardware module is configured to store weights corresponding to a matrix and to perform a vector-matrix multiplication (VMM) for the matrix. The GP processor is configured to control the compute engines, to receive output of the VMM for the matrix from the compute engines, and to perform a nonlinear operation on the output. The compute engines are addressable by data movement initiators. Data may be moved to and/or from the compute engines in data paths that bypass the GP processor.


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