Fpga wide barrel-shifters implementation using packed dsp multipliers

Abstract

Barrel-shifters may be implemented in field programmable gate array (FPGA) using digital signal processor (DSP) multipliers, rather than consuming lookup table (LUT) resources. This advantageously uses otherwise under-utilized assets, leaving previously heavily-burdened LUT resources available for other uses. Building blocks of 8-bit and 4-bit DSP-based shifters are implemented in parallel sets for wide data and in tandem stages for larger shifts. For example, a 32-bit barrel-shifter may be implemented using a set of seven (7) parallel 8-bit shifters to handle the width of the data in a first stage and another set of eight (8) parallel 4-bit shifters in a second stage that operates in tandem with the first stage, to complete the shift. In an example, the first stage provides fine shifting and the second stage provides coarse shifting. To achieve even wider barrel-shifters, for example a 256-bit shifter, 32-bit barrel-shifter may be used recursively.