The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Jun. 06, 2024
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Sung Lae Oh, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 25/065 (2023.01); H10B 43/27 (2023.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/762 (2013.01); H01L 21/76802 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H10B 43/27 (2023.02); H10D 62/115 (2025.01);
Abstract

A method for manufacturing a semiconductor device comprises: forming isolation layers in a front surface of an upper wafer substrate; forming a through hole that exposes one of the isolation layers, through the upper wafer substrate from a back surface of the upper wafer substrate; forming a first dielectric layer that fills the through hole; defining a lower wafer including a lower wafer substrate, a second dielectric layer defined on the lower wafer substrate, and a first wiring line disposed in the second dielectric layer; bonding a top surface of the second dielectric layer and a bottom surface of the first dielectric layer; forming a third dielectric layer on the front surface of the upper wafer substrate; forming a through via that passes through the third dielectric layer, the one isolation layer, the first dielectric layer; and forming a second wiring line coupled to the through via.


Find Patent Forward Citations

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Oh, Sung. (2026). Semiconductor device having wafer-to-wafer bonding structure and manufacturing method thereof (U.S. Patent No. 12532754). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12532754

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