The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Dec. 01, 2021
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Rakesh Chand, Singapore, SG;

Muniandy Shunmugam, Singapore, SG;

Ramachandramurthy Pradeep Yelehanka, Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 41/23 (2013.01); B81B 7/00 (2006.01); H10N 30/02 (2023.01); H10N 30/20 (2023.01); H10N 30/30 (2023.01); H10N 30/85 (2023.01);
U.S. Cl.
CPC ...
H10N 30/02 (2023.02); B81B 7/0032 (2013.01); H10N 30/20 (2023.02); H10N 30/302 (2023.02); H10N 30/85 (2023.02); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0271 (2013.01);
Abstract

A method of fabricating a semiconductor substrate includes the following steps. A first wafer is provided and a first surface of the first wafer is etched to form a plurality of cavities. A second wafer is formed on the first surface, where forming the second wafer includes the following steps: providing a core substrate; forming a first insulating layer on the core substrate; and depositing a polysilicon layer on the first insulating layer and the core substrate. In addition, the polysilicon layer is bonded with the first wafer to cover the cavities, where the polysilicon layer is disposed between the first insulating layer and the first wafer. In addition, a semiconductor substrate and MEMS devices using the semiconductor substrate are also provided.


Find Patent Forward Citations

Loading…