The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Feb. 21, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jeon Il Lee, Suwon-si, KR;

Min Hee Cho, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 51/10 (2023.01); H10B 51/40 (2023.01); H10D 64/68 (2025.01);
U.S. Cl.
CPC ...
H10B 51/20 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 51/10 (2023.02); H10B 51/40 (2023.02); H10D 64/689 (2025.01);
Abstract

A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.


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