The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Sep. 19, 2023
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Calogero Marco Ippolito, Aci Castello, IT;

Michele Vaiana, San Giovanni La Punta, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/00 (2006.01); H03M 1/12 (2006.01); H03M 3/00 (2006.01);
U.S. Cl.
CPC ...
H03M 1/1255 (2013.01); H03M 1/1215 (2013.01); H03M 3/454 (2013.01); H03M 3/462 (2013.01);
Abstract

A differential pair of FETs forms a sensor circuit coupled to a differential current reading circuit that includes a current to voltage converter and an analog to digital converter. An ESD protection circuit interposed between the sensor circuit and the differential current reading circuit adds spurious currents to a differential sensor current output by the sensor circuit. A circuit before the ESD protection circuit switches the sign of the differential sensor current according to a period of complementary phase clock signals which correspond to a sampling interval of the analog to digital converter. A circuit selects signals depending on the value of the period of the phase clock signals to eliminate the spurious currents.


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