The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Apr. 27, 2023
Applicant:

Hewlett Packard Enterprise Development Lp, Spring, TX (US);

Inventors:

Rachid Kadri, Houston, TX (US);

Michael Chan, Bellaire, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H03K 19/20 (2006.01); H03M 1/78 (2006.01);
U.S. Cl.
CPC ...
H03K 19/173 (2013.01); H03K 19/20 (2013.01); H03M 1/785 (2013.01);
Abstract

One aspect provides a programmable logic device. The device includes an input circuit for detecting a multi-level input signal and an output circuit. The input circuit includes: an input pin for receiving the multi-level input signal; first and second programmable voltage generators to generate, respectively, first and second multi-level voltage signals; a pair of comparators, each comparator having a first input coupled to the input pin and a second input coupled to a corresponding programmable voltage generator; and a logic gate coupled to the comparators, thereby facilitating the detection of the multi-level input signal based on outputs of the comparators. The output circuit includes a third programmable voltage generator to generate a third multi-level voltage signal, an output pin, and a voltage buffer coupling the third programmable voltage generator to the output pin, thereby facilitating the programmable logic device to output, over the output pin, the third multi-level voltage signal.


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