The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Mar. 16, 2021
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Kei Takahashi, Kanagawa, JP;

Takayuki Ikeda, Kanagawa, JP;

Shuji Fukai, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/72 (2006.01); H03F 3/217 (2006.01); H10D 84/03 (2025.01); H10D 84/80 (2025.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H03F 3/72 (2013.01); H03F 3/2171 (2013.01); H10D 84/038 (2025.01); H10D 84/811 (2025.01); H10D 88/01 (2025.01); H03F 2203/7227 (2013.01);
Abstract

A small semiconductor device is provided. A semiconductor device with low power consumption is provided. A semiconductor device with a high degree of integration is provided. The semiconductor device includes a first transistor, an insulating layer over the first transistor, a conductive layer, and a gate driver; part of the conductive layer is provided to be embedded in the insulating layer; the gate driver includes a second transistor and a third transistor; the second transistor and the third transistor are stacked and provided over the first transistor; the second transistor and the third transistor each contain a metal oxide in a channel formation region; one of a source and a drain of the second transistor and one of a source and a drain of the third transistor are electrically connected to a gate of the first transistor through the conductive layer; the gate driver is supplied with a first potential and a second potential; and the gate driver has a function of selecting the first potential or the second potential and supplying the selected potential to the gate of the first transistor.


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