Chiplet-based hierarchical tree topology architecture for neuromorphic computing

Abstract

This application describes chiplet-based neuromorphic systems, devices, and chips. An exemplary chiplet-based neuromorphic system may include: a plurality of neuron processing entities (NPE); a plurality of chiplets each comprising a plurality of switches and a group of NPEs from the plurality of NPEs; and a plurality of interposers each comprising a plurality of routers and a group of chiplets from the plurality of chiplets; wherein each of the plurality of switches within each chiplet connects to one or more of the group of NPEs, and the plurality of switches within the each chiplet are organized in a tree topology; wherein each of the plurality of routers within each interposers connects to one or more of the group of chiplets, and the plurality of routers within the each interposer are organized in a tree topology.