The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2026

Filed:

Mar. 30, 2022
Applicant:

Amazon Technologies, Inc., Seattle, WA (US);

Inventors:

Jiading Gai, Seattle, WA (US);

Tobias Joseph Kastulus Edler Von Koch, Austin, TX (US);

Robert Geva, Cupertino, CA (US);

Paul Gilbert Meyer, Jericho, VT (US);

Donald John Kretsch, Cupertino, CA (US);

Ron Diamant, San Jose, CA (US);

Assignee:

Amazon Technologies, Inc., Seattle, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/44 (2018.01); G06F 8/41 (2018.01); G06N 3/082 (2023.01);
U.S. Cl.
CPC ...
G06F 8/447 (2013.01); G06F 8/451 (2013.01); G06N 3/082 (2013.01); G06F 8/433 (2013.01);
Abstract

A technique for arranging matrix multiplications for concurrent execution in an integrated circuit device may include obtaining a representation of a data dependency graph of a neural network model. The data dependency graph may include having an accumulation group (AG) pack of accumulation groups (AGs), in which each of the AGs has one or more matrix multipartition instructions. A representation of a memory location base partition constraint graph of the AG pack can be generated, and an AG row group constraint graph can be generated based on the memory location base partition constraint graph. The AGs of the AG pack can then be assigned to tiles in an integrated circuit device based on the AG row group constraint graph.


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