Methods of forming transistor interconnects on top of a semiconductor device substrate

Abstract

A method of forming transistor interconnects on top of a semiconductor device substrate, the method including: providing a semiconductor device substrate with CMOS transistors and an inter-layer dielectric atop the CMOS transistors; depositing a metal (Ni, Co, Ru, or Mo) catalyst layer atop the inter-layer dielectric; depositing a diffusion material including carbon atop the metal catalyst layer; then loading the substrate into a process chamber onto a heatable bottom platen; a heatable top platen applies a mechanical pressure to the substrate; and then forming graphene disposed at an interface of the inter-layer dielectric and the metal catalyst layer, and where the process chamber is a part of a modified or unchanged commercial bonding tool, hot-press tool, or pressure and temperature-controlled reactor.