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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12527175 B1

PDFFull Text
Date of Patent:
Jan. 13, 2026

Filed:

Aug. 06, 2021

Display substrate and display device

Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Linhong Han, Beijing, CN;

Yi Zhang, Beijing, CN;

Assignees:

Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan, CN;

BOE Technology Group Co., Ltd., Beijing, CN;

Attorney:

IPro, PLLC

Primary Examiner:

Bumsuk Won

Int. Cl.
CPC ...
H10K 59/131 (2023.01); G11C 19/28 (2006.01); H10K 59/121 (2023.01); H10K 59/65 (2023.01); H10K 59/80 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); G11C 19/28 (2013.01); H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/873 (2023.02); H10K 59/12 (2023.02); H10K 59/65 (2023.02); H10K 59/8731 (2023.02);
Abstract

A display substrate and a display device. The display substrate includes: a base substrate, which comprises a display region, a peripheral region and a barrier region, where the peripheral region surrounds the display region, and the display region surrounds the barrier region; a through hole located in the barrier region, the center of the display substrate not coinciding with the center of the through hole; a plurality of sub-pixels located in the display region; a plurality of signal lines that are located in the display region, the peripheral region and the barrier region, and are electrically connected to the plurality of sub-pixels; a shift register circuit that is located in the peripheral region and is electrically connected to the plurality of signal lines; and at least one circle of crack detection lines that are located in the barrier region and surround the through hole.

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