logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12527159 B1

PDFFull Text
Date of Patent:
Jan. 13, 2026

Filed:

Aug. 01, 2022

Display apparatus and method of manufacturing the same

Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Hyun Kim, Yongin-si, KR;

Seulki Kim, Yongin-si, KR;

Kapsoo Yoon, Yongin-si, KR;

Woogeun Lee, Yongin-si, KR;

Seungha Choi, Yongin-si, KR;

Yeeun Kang, Yongin-si, KR;

Shoyeon Kim, Yongin-si, KR;

Seungrae Kim, Yongin-si, KR;

Donghyun Won, Yongin-si, KR;

Kwangsoo Lee, Yongin-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:

Innovation Counsel LLP

Primary Examiner:

Chad M Dicke

Assistant Examiner:

Dave undefined Tan

Int. Cl.
CPC ...
H10K 59/121 (2023.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/12 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10K 59/1201 (2023.02);
Abstract

A display apparatus includes a semiconductor layer arranged on a substrate and including a channel area and a source area and a drain area respectively arranged at both sides of the channel area, the semiconductor layer including an opening portion arranged to be adjacent to one of the source area and the drain area, an electrode overlapping in a plan view and electrically connected to one of the source area and the drain area, and an insulating pattern arranged between the semiconductor layer and the electrode, wherein a first edge of the electrode adjacent to the opening portion is spaced apart from the opening portion, and an edge portion of the insulating pattern adjacent to the opening portion is spaced apart from the opening portion.

Find Patent Forward Citations

Loading…