The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Oct. 06, 2022
Applicants:

Samsung Display Co., Ltd., Yongin-si, KR;

Industry-university Cooperation Foundation Hanyang University Erica Campus, Ansan-si, KR;

Inventors:

Joon Seok Park, Yongin-si, KR;

Saeroonter Oh, Seoul, KR;

Ki Hwan Kim, Anyang-si, KR;

Myounghwa Kim, Seoul, KR;

Min Goo Kim, Seoul, KR;

Jun Hyung Lim, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H01L 51/56 (2006.01); H10D 30/67 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10K 59/121 (2023.01); H10K 59/123 (2023.01); H10K 59/12 (2023.01); H10K 59/124 (2023.01); H10K 71/00 (2023.01);
U.S. Cl.
CPC ...
H10D 30/6757 (2025.01); H10D 86/0231 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01); H10K 59/1213 (2023.02); H10K 59/123 (2023.02); H10K 59/1201 (2023.02); H10K 59/124 (2023.02); H10K 71/00 (2023.02);
Abstract

A display device includes: a substrate; a barrier layer on the substrate, and including: a trench area recessed in a direction towards the substrate; and a flat area surrounding the trench area, and having a flat upper surface; and a switching transistor and a driving transistor on the barrier layer. The switching transistor includes: a first active layer on the barrier layer, at least a portion of the first active layer being located at the trench area, the first active layer including a channel area, and a source area and a drain area at opposite sides of the channel area; a first gate electrode on the first active layer; and a first upper electrode and a second upper electrode on and connected to the first active layer.


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