Semiconductor memory device with mold insulating patterns, semiconductor patterns, and gate electrodes

Abstract

According to some embodiments of the present inventive concept, a semiconductor memory device includes a plurality of mold insulating layers on a substrate and spaced apart from one another, a plurality of semiconductor patterns which are between respective ones of the plurality of mold insulating layers adjacent to each other, a plurality of gate electrodes, on respective ones of the plurality of semiconductor patterns, an information storage element which includes a first electrode electrically connected to each of the plurality of semiconductor patterns, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line on the substrate and contacts the semiconductor pattern, and an insulating buffer film between the first electrodes and the second electrode and on a sidewall of a respective one of the plurality of mold insulating layers.