The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Feb. 17, 2022
Applicant:

Sony Semiconductor Solutions Corporation, Atsugi, JP;

Inventors:

Noam Eshel, Stuttgart, DE;

Golan Zeituni, Stuttgart, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 25/59 (2023.01); G01S 7/4865 (2020.01); G01S 17/894 (2020.01); G01S 17/931 (2020.01); H04N 25/57 (2023.01); H04N 25/771 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01); H10F 39/00 (2025.01);
U.S. Cl.
CPC ...
H04N 25/59 (2023.01); G01S 7/4865 (2013.01); G01S 17/894 (2020.01); G01S 17/931 (2020.01); H04N 25/57 (2023.01); H04N 25/771 (2023.01); H04N 25/78 (2023.01); H04N 25/79 (2023.01); H10F 39/803 (2025.01);
Abstract

An image sensor assembly includes a pixel circuit including a charge storage structure and an amplification transistor. A load path of the amplification transistor is between an amplifier drain line and a pixel output node. A potential at a storage node of the charge storage structure controls the amplification transistor. An amplifier drain circuit is configured to pass a low potential to the amplifier drain line in a reset period and a high potential in a readout period. A transition from the low potential to the high potential is not before an end of the reset period and prior to a start of the readout period.


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