The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Sep. 26, 2022
Applicant:

Ampleon Netherlands B.v., Nijmegen, NL;

Inventors:

Zhi Geng, Nijmegen, NL;

Yi Zhu, Nijmegen, NL;

Assignee:

Ampleon Netherlands B.V., Nijmegen, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/68 (2006.01); H01L 23/66 (2006.01); H03F 1/02 (2006.01); H03F 1/56 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01); H03F 3/21 (2006.01);
U.S. Cl.
CPC ...
H03F 3/245 (2013.01); H01L 23/66 (2013.01); H03F 1/0288 (2013.01); H03F 1/565 (2013.01); H03F 3/195 (2013.01); H01L 2223/6611 (2013.01); H01L 2223/6655 (2013.01); H03F 3/211 (2013.01); H03F 2200/451 (2013.01);
Abstract

Example embodiments relate to power amplifiers and Doherty amplifiers that include the same. One example embodiment includes a power amplifier. The power amplifier includes one or more radiofrequency (RF) output terminals. The power amplifier also includes a Gallium Nitride (GaN) semiconductor die on which a power field-effect transistor (FET) is integrated. The FET includes a plurality of FET cells that are adjacently arranged in a row. The FET cells are connected either directly or indirectly to the one or more RF output terminals via a respective first inductor. For FET cells arranged at opposing ends of the row of FET cells, a total FET cell gate width and an inductance of the first inductor is larger and smaller than the total FET cell gate width and inductance of the first inductor for one or more FET cells arranged in the middle of the row of FET cells, respectively.


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