Load regulation for ldo with low loop gain

Abstract

Circuits and methods for maintaining loop stability and good load regulation in low loop gain LDO regulator circuits. Embodiments encompass LDO regulator circuits that include an offset error correction circuit that generates an opposing voltage Vas a function of load current to substantially cancel out variations in Vthat would otherwise occur due to load regulation limitations of the LDO regulator circuits. Embodiments use Vto imbalance currents in differential paths in a last-stage LDO error-amplifier so that an offset is propagated to a pair of inputs to the error-amplifier, thereby altering the output voltage Vto a corrected value. Benefits include improved LDO load regulation even when feedback loop gain is low, the available of both digital and analog implementations, high LDO accuracy and less variation of the output voltage V, and suitability for implementation in integrated circuits for applications such as high precision power supplies.