The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Dec. 12, 2022
Applicant:

Murata Manufacturing Co., Ltd., Nagaokakyo, JP;

Inventors:

Tatsuya Kitamura, Nagaokakyo, JP;

Koshi Himeda, Nagaokakyo, JP;

Takeshi Furukawa, Nagaokakyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 25/16 (2023.01); H01L 25/18 (2023.01); H02M 3/04 (2006.01); H05K 3/46 (2006.01); H10D 1/20 (2025.01); H10D 1/68 (2025.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H10D 1/20 (2025.01); H10D 1/68 (2025.01); H02M 3/04 (2013.01);
Abstract

A semiconductor composite device includes active elements and passive elements constituting a voltage regulator and disposed in association with a plurality of channels, a load to be supplied with a direct-current voltage regulated by the voltage regulator, and a wiring board electrically connected to the active elements, the passive elements, and the load. A plurality of capacitors disposed in the channels include an integrally formed capacitor array including a plurality of capacitor portions disposed in a plane. The capacitor array includes a plurality of through hole conductors extending through the capacitor array in a direction perpendicular to a mounting surface of the wiring board. At least a part of the capacitor array is positioned to overlap the load when viewed from the mounting surface of the wiring board.


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