The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Mar. 01, 2021
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Kazuaki Ohshima, Atsugi, JP;

Hitoshi Kunitake, Isehara, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/538 (2006.01); H03K 19/094 (2006.01); H10D 30/67 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/5386 (2013.01); H03K 19/094 (2013.01); H10D 30/6755 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01);
Abstract

A semiconductor device being capable of high-speed data transmission and having a reduced circuit area is provided. The semiconductor device includes a semiconductor chip, an external terminal, and a layer including two facing surfaces. The semiconductor chip is provided on one surface side of the layer, and the external terminal is provided on the other surface side of the layer at least in a region not overlapping with the semiconductor chip. The semiconductor chip includes a first circuit including a first transistor, and the layer includes a second circuit including a second transistor. The first circuit is electrically connected to the second circuit, and the second circuit is electrically connected to the external terminal. The second transistor includes a metal oxide in a channel formation region. Note that the second circuit may be a CML circuit. In addition, an insulator may be provided above the one surface of the layer and on a side surface of the semiconductor chip.


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