The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Sep. 22, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minki Kim, Suwon-si, KR;

Seungduk Baek, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01);
U.S. Cl.
CPC ...
H01L 24/08 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05017 (2013.01); H01L 2224/05018 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05541 (2013.01); H01L 2224/05557 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/05576 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/0603 (2013.01); H01L 2224/06102 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/08225 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01);
Abstract

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.


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