The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Jun. 07, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Devanathan Varadarajan, Allen, TX (US);

Varun Singh, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/16 (2006.01); G11C 29/40 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 29/4401 (2013.01); G11C 29/16 (2013.01); G11C 29/40 (2013.01);
Abstract

Circuits and methods are directed to repairable memory systems and memory repair processes. An example circuit includes first and second logic coupled together. The first logic receives a plurality of instances of defect data from a plurality of memories, respectively, in which each of the plurality of instances of defect data has a memory-specific format. The first logic converts each of the plurality of instances of defect data to a common format and merges the plurality instances of defect data in the common format to generate merged data. The second logic receives the merged data and determines a plurality of instances of repair data for the plurality of instances of defect data, respectively, based on the merged data.


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