Memory device and operating method of the memory device

Abstract

A memory device, and an operating method of the memory device, includes a voltage generator for generating operating voltages and a row decoder for transmitting the operating voltages to a memory block through local lines. The memory device also includes page buffers connected to the memory block through bit lines, the page buffers applying voltages to the bit lines in response to page buffer control signals. The memory device further includes a page buffer control circuit for outputting the page buffer control signals by adjusting levels of the voltages and times at which the voltages are applied to the bit lines according to distances of the bit lines from the row decoder.