The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Mar. 10, 2024
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jaehyeok Baek, Suwon-si, KR;

Sungyong Cho, Suwon-si, KR;

Hyeran Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 11/4099 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4076 (2013.01); G11C 11/4093 (2013.01); G11C 11/4099 (2013.01); G11C 2207/2254 (2013.01);
Abstract

A memory device includes a data input/output (I/O) pin, an output driver, a multi-level receiver and a calibrator. The output driver is connected to the data I/O pin, and generates an internal input signal based on a first clock signal. The multi-level receiver is connected to the data I/O pin, and includes a plurality of samplers. The plurality of samplers generate a plurality of decision signals by sampling the internal input signal based on a reference voltage and a second clock signal. The calibrator detects and compensates at least one of timing skew and offset associated with the plurality of samplers based on the plurality of decision signals. The internal input signal is a multi-level signal having three or more voltage levels that are different from each other.


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