The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Sep. 29, 2023
Applicant:
Everspin Technologies, Inc., Chandler, AZ (US);
Inventors:
Syed M. Alam, Austin, TX (US);
Jacob T. Williams, Austin, TX (US);
Assignee:
Everspin Technologies, Inc., Chandler, AZ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3185 (2006.01); G11C 11/16 (2006.01); H03K 3/037 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G01R 31/318525 (2013.01); G01R 31/318536 (2013.01); G01R 31/318552 (2013.01); G11C 11/1673 (2013.01); G11C 11/1693 (2013.01); H03K 3/037 (2013.01); H03K 19/20 (2013.01);
Abstract
A scan chain circuitry for a memory device includes a first non-volatile storage bit (nvbit) configured to receive a shared control signal, a second nvbit configured to receive the shared control signal, a first flip-flop connected to the first nvbit, and a second flip-flop connected to the second nvbit and the first flip-flop. The first flip-flop enables loading a first data in (din) to the first nvbit based on a clock signal, and the second flip-flop enables loading a second din to the second nvbit based on the clock signal.