The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Feb. 06, 2024
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Ingu Han, Paju-si, KR;

Soohong Choi, Paju-si, KR;

Hongjae Shin, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/038 (2013.01); G09G 3/3233 (2016.01); G09G 3/3266 (2016.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H10K 59/80 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3233 (2013.01); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 59/873 (2023.02); G09G 2300/0408 (2013.01); G09G 2300/0842 (2013.01);
Abstract

A display panel and a display device which may remove load deviation between clock signal lines. More specifically, the display device includes a substrate including a display area capable of displaying an image and a non-display area disposed around the display area, the display area including a subpixel and a gate line for driving the subpixel; a gate driving panel circuit disposed in the non-display area and configured to output a gate signal to the gate line; a plurality of clock signal lines disposed in the non-display area and positioned to be farther from the display area than the gate driving panel circuit to supply a plurality of clock signals to the gate driving panel circuit; an overcoat layer disposed on the plurality of clock signal lines and the gate driving panel circuit; and a light emitting element included in the subpixel, comprising a cathode electrode disposed on the overcoat layer and extending from the display area to the non-display area, wherein the cathode electrode is disposed not to overlap the plurality of clock signal lines.


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