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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12524595 B1

PDFFull Text
Date of Patent:
Jan. 13, 2026

Filed:

Sep. 09, 2022

Methods for vfet cell placement and cell architecture

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jung Ho Do, Hwaseong-si, KR;

Seung Hyun Song, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Sughrue Mion, PLLC

Primary Examiner:

Marcos D Pizarro

Int. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 30/63 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/83 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 23/5286 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/024 (2025.01); H10D 30/0243 (2025.01); H10D 30/62 (2025.01); H10D 30/63 (2025.01); H10D 62/151 (2025.01); H10D 64/252 (2025.01); H10D 84/0193 (2025.01); H10D 84/0195 (2025.01); H10D 84/837 (2025.01); H10D 84/85 (2025.01); H10D 84/853 (2025.01); H10D 89/10 (2025.01);
Abstract

A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1cell and a 2cell placed next to each other in a cell width direction, wherein the 1cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1cell, and connects a vertical field-effect transistor (VFET) of the 1cell to a power rail of the 1cell, wherein a 2cell includes a connector connected to a power rail of the 2cell, wherein the fin of the 1cell and the connector of the 2cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1cell and the connector of the 2cell are merged.

Find Patent Forward Citations

Do, Jung. (2026). Methods for vfet cell placement and cell architecture (U.S. Patent No. 12524595). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12524595

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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