The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Mar. 07, 2023
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

John Thomas Monk, Palo Alto, CA (US);

Kartik Mohanram, Pittsburgh, PA (US);

Ramana Rao Kompella, Cupertino, CA (US);

Sundar Iyer, Palo Alto, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); H04L 41/0631 (2022.01); H04L 43/065 (2022.01); H04L 43/0823 (2022.01);
U.S. Cl.
CPC ...
G06F 11/0712 (2013.01); H04L 41/0631 (2013.01); H04L 41/065 (2013.01); H04L 43/065 (2013.01); H04L 43/0823 (2013.01);
Abstract

Systems, methods, and computer-readable media for fault code aggregation across application-centric dimensions. In an example embodiment, a system obtains respective fault codes corresponding to one or more network devices in a network and maps the one or more network devices and/or the respective fault codes to respective logical policy entities defined in a logical policy model of the network, to yield fault code mappings. The system aggregates the one or more of the fault code mappings along respective logical policy dimensions in the network to yield an aggregation of fault codes across respective logical policy dimensions and, based on the aggregation, presents, for each of the respective logical policy dimensions, one or more hardware-level errors along the respective logical policy dimension.


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