The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Nov. 10, 2021
Xilinx, Inc., San Jose, CA (US);
Ming Ruan, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Multiplication of integers over a finite field involves an array of arithmetic circuits configured to input a-limbs, d-limbs, and r-limbs. The array determines an intermediate term, Z, having z-limbs 0 through K by determining respective sets of intermediate z-limbs 0 through K−1 for r-limbs i for i=0 to K−1, and summing corresponding ones of the intermediate z-limbs of sets i through K−1. The arithmetic circuits determine for r-limb 0, intermediate z-limbs 0 through K−1 of set 0 as products of r-limb 0 and a-limbs 0 through K−1, and for the remaining r-limbs determines intermediate z-limbs using different combinations of a-limbs, r-limbs, modulus, and d-limbs. A modulo circuit computes Gas (most significant M bits of Z*m)+(least significant Q bits of Z, wherein Mis a number of bits by which a number of bits of Z exceeds N, and Q is equal to M+ceil (logm), and increases G by m if bits Q through N−1 of Z all having bit value one, and G≥2−m. Circuitry assigns bits G bits 0 through Q−1 to Y bits 0 through Q−1, and G bit Q to Y bit Q.