The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2026
Filed:
Mar. 13, 2024
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Derui Kong, Irvine, CA (US);
Wei Zhang, Irvine, CA (US);
Seong-Ho Lee, Aliso Viejo, CA (US);
Sanghye Chung, Irvine, CA (US);
Delong Cui, Tustin, CA (US);
Jingguang Wang, Laguna Niguel, CA (US);
Kambiz Vakilian, Irvine, CA (US);
Jun Cao, Irvine, CA (US);
Avago Technologies International Sales Pte. Limited, Singapore, SG;
Abstract
A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.