The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2026

Filed:

Mar. 22, 2024
Applicant:

Hkc Corporation Limited, Guangdong, CN;

Inventors:

Yao Li, Guangdong, CN;

Tianjun Huang, Guangdong, CN;

Zhonglin Cao, Guangdong, CN;

Chuan Wu, Guangdong, CN;

Lidan Ye, Guangdong, CN;

Assignee:

HKC CORPORATION LIMITED, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1368 (2006.01); G02F 1/1343 (2006.01); G02F 1/1347 (2006.01);
U.S. Cl.
CPC ...
G02F 1/1368 (2013.01); G02F 1/134309 (2013.01); G02F 1/1347 (2013.01);
Abstract

A display device including three sequentially stacked layers of cholesteric liquid crystal cell, where each layer of cholesteric liquid crystal cell includes a cholesteric liquid crystal layer and a first electrode layer and a second electrode layer arranged on two sides of the cholesteric liquid crystal layer respectively, the first electrode layer includes multiple first electrode strips, the second electrode layer includes multiple second electrode strip, along a thickness direction of the three layers of cholesteric liquid crystal cell, the first electrode strips from different first electrode layers are disposed one to one and electrically connected, and the second electrode strips from different second electrode layers are disposed one to one and connected in parallel; the display device further includes an array transistor layer, and each of the second electrode strips in the three layers of cholesteric liquid crystal cell is connected in series with the array transistor layer.


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