The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Mar. 08, 2022
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Kenichi Matsushita, Nonoichi Ishikawa, JP;

Mitsuhiko Kitagawa, Nomi Ishikawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/60 (2025.01); H10D 8/00 (2025.01); H10D 12/00 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 84/617 (2025.01); H10D 8/422 (2025.01); H10D 12/481 (2025.01); H10D 62/393 (2025.01);
Abstract

A semiconductor device includes: a first semiconductor layer located in a diode region, the first semiconductor layer including a plurality of first semiconductor regions and a plurality of second semiconductor regions alternately arranged in a first direction; a second semiconductor layer located in the IGBT region; and a third semiconductor layer located on the first semiconductor layer in the diode region, an impurity concentration of the third semiconductor layer having a maximum at a first position in a second direction, an impurity concentration of the first semiconductor region having a maximum at a second position in the second direction, a third position being separated from the upper surface of the first electrode by a length that is 3 times a distance between the second position and a lower end of the third semiconductor layer, the first position being the same as or lower than the third position.


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