The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Sep. 07, 2021
Applicant:

Innoscience (Suzhou) Technology Co., Ltd., Suzhou, CN;

Inventors:

Ronghui Hao, Suzhou, CN;

Fu Chen, Suzhou, CN;

King Yuen Wong, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 62/85 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H10D 30/015 (2025.01); H10D 30/791 (2025.01); H10D 62/8503 (2025.01); H10D 64/518 (2025.01);
Abstract

A semiconductor device includes a first and a second nitride-based semiconductor layers, a source electrode, a drain electrode, a passivation layer, a stress modulation layer and a gate electrode. The stress modulation layer is disposed over the second nitride-based semiconductor layer and extends along at least one sidewall of the passivation layer to make contact with the second nitride-based semiconductor layer, so as to form an interface. The gate electrode is disposed over the stress modulation layer and between the source and drain electrodes. The gate electrode is located directly above the interface of the stress modulation layer and the second nitride-based semiconductor layer.


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