The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2026
Filed:
Oct. 23, 2023
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventor:
Brian Matthew Zimmer, Sunnyvale, CA (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 7/033 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0091 (2013.01); H04L 7/0331 (2013.01);
Abstract
Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.